In liquid crystal display (LCD) TVs the power system needs to supply DC voltages for the electronic circuitry of the TV and further provide a controllable power to drive the light emitting diode (LED) backlight unit. A popular architecture presently used is to supply both the DC voltage and the LED power from a single power transformer, thus saving the cost of additional power transformers and the associated primary side drive stage. In such an approach the primary side power stage control is usually utilized to provide regulation for the main DC output voltage. In such an architecture, since the power supplied to the LED drive stage is thus not well regulated, a separate LED drive circuit has to be deployed to control the LED current as well as any dimming operation. A technique has been developed to drive the LED string(s) with a switching device with its one switching edge synchronized with the primary side switching action and regulate the LED current by modulating its conduction pulse width, as described in U.S. Pat. No. 8,779,686 issued Jul. 15, 2014 to Jin, to which the present application claims priority, the entire contents of which is incorporated herein by reference.
FIGS. 1 and 2 herein illustrate typical circuit examples of such a technique, with FIG. 1 showing an application example with a fly back topology on the primary side, and FIG. 2 showing a half bridge LLC topology on the primary side. In the example circuits illustrated in FIGS. 1 and 2, the energy storage capacitor, inductor and freewheel diode of a conventional secondary side buck or boost circuit are removed, hence yielding a significant cost savings.
Particularly, FIG. 1 illustrates a high level schematic diagram of an LED driving arrangement 10 comprising: an inductance element 20, illustrated and described herein as a transformer 20 and comprising a primary winding 30 and a secondary winding 40 magnetically coupled to primary winding 30; a switching circuit 50, switching circuit 50 comprising a primary side electronically controlled switch Q1, illustrated and described herein as an n-channel metal-oxide-semiconductor field-effect-transistor (NFET) Q1; a unidirectional electronic valve D1, illustrated and described herein as a diode D1; a capacitive element C1, illustrated and described herein as a capacitor C1; a secondary side electronically controlled switch Q2, illustrated and described herein as an NFET Q2; an LED based luminaire 60, illustrated and described herein as an LED string 60; and a control circuitry 70.
A first end of primary winding 30 is coupled to a power lead and a second end of primary winding 30, whose polarity is denoted with a dot, is coupled to the drain of NFET Q1. The source of NFET Q1 is coupled to a return lead and the gate of NFET Q1 is coupled to a respective output of control circuitry 70 (connection not showed). A first end of secondary winding 40, whose polarity is denoted with a dot, is coupled to the anode of diode D1 and the cathode of diode D1 is coupled to a first end of capacitor C1 and the anode end of LED string 60. A second end of capacitor C1 and the cathode end of LED string 60 are commonly coupled to the drain of NFET Q2. The gate of NFET Q2 is coupled to a respective output of control circuitry 70 (connection not shown). The source of NFET Q2 and the second end of secondary winding 40 are each coupled to a common potential. The common potential is further coupled to the metal chassis of a device. Further illustrated is the parasitic capacitance generated between LED string 60 and the metal chassis, the parasitic capacitance denoted CS.
In operation, control circuitry 70 is arranged to alternately switch NFET Q1 between an open state and a closed state. When NFET Q1 is in a closed state, transformer 20 is charged. When NFET Q2 is opened, the charge of transformer 20 is output at secondary winding 40 due to the opposing polarities of primary winding 30 and secondary winding 40. Control circuitry 70 is further arranged to alternately switch NFET Q2 between an open state and a closed state in order to maintain a desired voltage across LED string 60. When NFET Q2 is in a closed state, the power output at secondary winding is provided to LED string 60 and capacitor C1. As a result, current flows through LED string 60 and light is emitted. When NFET Q2 is in an open state there is no current path through LED string 60.
This works well under many application circumstances. However, a particular issue occurs when LED string 60 bears a large parasitic capacitance CS and such parasitic capacitance is loaded to the regulating NFET Q2. As described above, parasitic capacitance CS exists between LED string 60 and the metal chassis when LED string 60 is installed tightly onto the metal chassis, in most occasions to utilize the metal chassis as a heat sink. When the ground of the LED drive circuit is connected to the metal chassis, as described above, the parasitic capacitance is loaded to the switching loop of NFET Q2. Particularly, when NFET Q2 is opened parasitic capacitance CS is charged by the power output at secondary winding 40, and no discharge path is provided. When NFET Q2 is then closed, a current spike will occur due to the discharge of CS through LED string 60 and NFET Q2. This result is different from the charging of the LED string 60 current at turn on of NFET Q2, since at turn on edge the current rising rate dI/dt is limited by the inductance of secondary winding 40 of transformer 20, whereas the discharge spike of parasitic capacitance CS shows a sharp wave shape due to the lack of dI/dt limiting element in the discharging path. This current spike may be sufficient to damage one or more of NFET Q2 and LED string 60.
Similarly, FIG. 2 illustrates a high level schematic diagram of an LED driving arrangement 100 comprising: an inductance element 120, illustrated and described herein as a transformer 120 and comprising a primary winding 130 and a secondary winding 140 magnetically coupled to primary winding 130; a switching circuit 150, switching circuit 150 comprising a first primary side electronically controlled switch Q3, illustrated and described herein as an NFET Q3 and a second primary side electronically controlled switch Q4, illustrated and described herein as an NFET Q4; a capacitance element CX, illustrated and described herein as a capacitor CX; a unidirectional electronic valve D2, illustrated and described herein as a diode D2; a unidirectional electronic valve D3, illustrated and described herein as a diode D3; a capacitor C1; an NFET Q2; an LED string 60; and a control circuitry 160.
The drain of NFET Q3 is coupled to a power lead and the gate of NFET Q3 is coupled to a respective output of control circuitry 160 (the connection not shown). The source of NFET Q3 is coupled to the drain of NFET Q4 and a first end of capacitor CX. A second end of capacitor CX is coupled to a first end of primary winding 130. A second end of primary winding 130 is coupled to the source of NFET Q4 and a return lead. The gate of NFET Q3 and the gate of NFET Q4 are each coupled to a respective output of control circuitry 160 (the connection not shown).
A first end of secondary winding 140 is coupled to the anode of diode D2 and a second end of secondary winding 140 is coupled to the anode of diode D3. The cathodes of diode D2 and diode D3 are commonly coupled to the first end of capacitor C1 and the anode end of LED string 60. The second end of capacitor C1 and the cathode end of LED string 60 are commonly coupled to the drain of NFET Q2. The gate of NFET Q2 is coupled to a respective output of control circuitry 160. The source of NFET Q2 and a center tap of secondary winding 140 are each coupled to a common potential. The common potential is further coupled to the metal chassis, as described above in relation to LED driving arrangement 10. Parasitic capacitance CS is further illustrated, between the anode end of LED string 60 and the metal chassis, as described above.
In operation, control circuitry 160 is arranged to alternately switch each of NFETs Q3 and Q4 between an open state and a closed state, with a dead time insertion, while ensuring that NFETs Q3 and Q4 are not both in a closed state contemporaneously. When NFET Q3 is in a closed state, and NFET Q4 is in an open state, primary winding 130 is charged in a first direction and a power is output from a first half of secondary winding 140 via diode D2. When NFET Q4 is in a closed state, and NFET Q3 is in an open state, primary winding 130 is charged in the opposite direction and a power is output from a second half of secondary winding 140 via diode D3. Capacitor CX is arranged to balance the charge of primary winding 130 during the cycle.
Control circuitry 160 is further arranged to alternately switch NFET Q2 between an open state and a closed state in order to maintain a desired voltage across LED string 60. As described above, when NFET Q2 is in a closed state, the power output at secondary winding is provided to LED string 60 and capacitor C1, and parasitic capacitance CS is charged. As a result, current flows through LED string 60 and light is emitted. When NFET Q2 is in an open state, parasitic capacitance CS is left charged, with no discharge path, as described above. Thus, when NFET Q2 switches to a closed state, a current spike is created by the discharge of parasitic capacitance CS through the series path of LED string 60 and NFET Q2. This current spike may be sufficient to damage one or more of NFET Q2 and LED string 60.
What is desired, and not provided by the prior art, is an arrangement to reduce the effect of the parasitic capacitance in the switching operation that causes sharp discharging current spikes.